JEDEC JESD82
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 07/01/2000
JEDEC JESD8-12A.01
1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 – 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 09/01/2007
JEDEC JESD82-32
DDR4 DATA BUFFER DEFINITION (DDR4DB01)
standard by JEDEC Solid State Technology Association,
JEDEC JS 9702
IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)
standard by JEDEC Solid State Technology Association, 06/01/2004
JEDEC JESD8-22A
HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
standard by JEDEC Solid State Technology Association, 10/01/2012
JEDEC JESD22-B110B
Mechanical Shock – Component and Subassembly
standard by JEDEC Solid State Technology Association, 07/01/2013
JEDEC JEP65 (R1999)
TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS
standard by JEDEC Solid State Technology Association, 12/01/1967
JEDEC JESD79-3-3
Addendum No. 1 to 3D Stacked SDRAM
Amendment by JEDEC Solid State Technology Association, 12/01/2013
JEDEC JESD22-A115C
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)
standard by JEDEC Solid State Technology Association, 11/01/2010
JEDEC JEP 155
RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION
standard by JEDEC Solid State Technology Association, 08/01/2008
JEDEC JESD84-B42
MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, HIGH CAPACITY (MMCA, 4.2)
standard by JEDEC Solid State Technology Association, 07/01/2007
JEDEC JESD209-4B
Low Power Double Data Rate 4 (LPDDR4)
standard by JEDEC Solid State Technology Association, 02/01/2017