JEDEC JESD75-1
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
standard by JEDEC Solid State Technology Association, 10/01/2001
NACE ASAE-ASABE B11 CGA ICC CTA
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE
standard by JEDEC Solid State Technology Association, 10/01/2001
ACCELERATED MOISTURE RESISTANCE – UNBIASED AUTOCLAVE
standard by JEDEC Solid State Technology Association, 11/01/2010
METAL PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES AND COVERS
standard by JEDEC Solid State Technology Association, 04/01/1987
RECOMMENDED STANDARD FOR THYRISTORS
standard by JEDEC Solid State Technology Association, 06/01/1972
DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
standard by JEDEC Solid State Technology Association, 05/01/2007
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/2018
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
standard by JEDEC Solid State Technology Association, 11/01/2018
EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2004
SIGNATURE ANALYSIS
standard by JEDEC Solid State Technology Association, 07/01/1999
EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS
standard by JEDEC Solid State Technology Association, 02/01/2007
Byte Addressable Energy Backed Interface
standard by JEDEC Solid State Technology Association, 07/01/2017