JEDEC JP 002

CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE
standard by JEDEC Solid State Technology Association, 03/01/2006

JEDEC JESD89-1A

TEST METHOD FOR REAL-TIME SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 10/01/2007

JEDEC JESD213

STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) – LEAD (Pb) CONTENT
standard by JEDEC Solid State Technology Association, 03/01/2010

JEDEC JESD 47G.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2010

JEDEC JESD30E

DESCRIPTIVE DESIGNATION SYSTEM FOR SEMICONDUCTOR-DEVICE PACKAGES
standard by JEDEC Solid State Technology Association, 08/01/2008

JEDEC JESD13-B

STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES
standard by JEDEC Solid State Technology Association, 05/01/1980

JEDEC JESD210

AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORS
standard by JEDEC Solid State Technology Association, 12/01/2007

JEDEC JESD8-6

ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995

JEDEC JESD8-5A.01

ADDENDUM No. 5 to JESD8 – 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT
standard by JEDEC Solid State Technology Association, 09/01/2007

JEDEC JEP 106AA

STANDARD MANUFACTURERS IDENTIFICATION CODE
standard by JEDEC Solid State Technology Association, 04/01/2009