JEDEC JP 002

CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE
standard by JEDEC Solid State Technology Association, 03/01/2006

JEDEC JESD89-1A

TEST METHOD FOR REAL-TIME SOFT ERROR RATE
standard by JEDEC Solid State Technology Association, 10/01/2007

JEDEC JESD213

STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) – LEAD (Pb) CONTENT
standard by JEDEC Solid State Technology Association, 03/01/2010

JEDEC JESD22-A117E

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
standard by JEDEC Solid State Technology Association, 11/01/2018

JEDEC JESD 22-A111

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES
standard by JEDEC Solid State Technology Association, 05/01/2004

JEDEC JESD 47G.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 04/01/2010

JEDEC JESD30E

DESCRIPTIVE DESIGNATION SYSTEM FOR SEMICONDUCTOR-DEVICE PACKAGES
standard by JEDEC Solid State Technology Association, 08/01/2008

JEDEC JESD13-B

STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES
standard by JEDEC Solid State Technology Association, 05/01/1980

JEDEC JESD210

AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORS
standard by JEDEC Solid State Technology Association, 12/01/2007

JEDEC JESD8-6

ADDENDUM No. 6 to JESD8 – HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
standard by JEDEC Solid State Technology Association, 08/01/1995