JEDEC JESD 24-2 (R2002)
ADDENDUM No. 2 to JESD24 – GATE CHARGE TEST METHOD
Amendment by JEDEC Solid State Technology Association, 01/01/1991
NACE ASAE-ASABE B11 CGA ICC CTA
ADDENDUM No. 2 to JESD24 – GATE CHARGE TEST METHOD
Amendment by JEDEC Solid State Technology Association, 01/01/1991
ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Human Body Modal (HBM) – Component Level
standard by JEDEC Solid State Technology Association, 05/12/2017
TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES: Â
standard by JEDEC Solid State Technology Association, 05/01/1982
METHOD OF DIODE Q MEASUREMENT
standard by JEDEC Solid State Technology Association, 11/01/1981
METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS
standard by JEDEC Solid State Technology Association, 03/01/2006
3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
standard by JEDEC Solid State Technology Association, 11/01/2009
Potential Failure Mode and Effects Analysis (FMEA)
standard by JEDEC Solid State Technology Association, 04/01/2012
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES
standard by JEDEC Solid State Technology Association, 11/01/2016
GUIDELINES FOR PACKING AND LABELING OF INTEGRATED CIRCUITS IN UNIT CONTAINER PACKING
standard by JEDEC Solid State Technology Association, 02/01/2006
SALT ATMOSPHERE
standard by JEDEC Solid State Technology Association, 01/01/2004
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION)
standard by JEDEC Solid State Technology Association, 06/01/2001
Universal Flash Storage Host Controller Interface (UFSHCI)
standard by JEDEC Solid State Technology Association, 01/01/2018